Processing in memory is a next-generation computing architecture beyond the conventional von Neumann computing architecture, and FeFET has been widely studied as a promising computational memory device based on their fast operation speed, high reliability and C-MOS compatibility. Antonis lab is actively conducting various research to develop an optimal FeFET for performing multiply and accumulation (MAC) operations, which is the most primary calculations in machine learning. In detail, we are introducing key approaches covering material and device architecture to overcome current technological issues. Moreover, using various computing logic, we are demonstrating the FeFET-PIM array with a high energy efficiency, which is evaluated by the system-level simulation.

To realize low-power / high-density in-memory computing, we propose an unprecedented negative capacitance-charge trap flash (NC-CTF) memory based in-memory computing architecture. To stabilized the NC effect, it is necessary to form a HfO2 based reversible single-domain ferroelectric (RSFE) layer. The RSFE is caused by a flexoelectric effect and a surface effect, which generate a large internal field and surface polarization pinning. As a consequence, a recoverable NC effect can be achieved without using a bipolar electric field. The application of an AND flash-like cell layout and source-follower/charge-sharing VMM operation to high-performance NC-CTF has successfully demonstrated energy-efficient and high-throughput in-memory computing.

Modern computing technologies require significant computing power, huge storage capacity, and an expanded communication bandwidth owing to extensive applications that use huge amounts of data, such as machine learning and edge computing. To achieve high efficiency in power-delay-area parameters, considerable effort have been made to optimize both the processor and the memory capacity. Nonvolatile logic-in-memory (NV-LiM) has been proposed to prevent performance degradation due to intra-chip global wires, by locating non-volatile memory in logic and eliminating standby power consumption during power-gating. Among them, unlike other NV memory devices, the hafnia-based FeFET shows three-terminal amplifying characteristics and selector functionality, demonstrating a high Ion/Ioff ratio and implementing CMOS logic without requiring additional switch devices.

We experimentally demonstrated high performance and self-rectifying hafnia based ferroelectric tunnel junction (FTJ) using stress engineering, diffusion barrier technology, and imprint field effect for neuromorphic computing and logic in memory application. In TiN/HZO/TaN/W stacked FTJ, W bottom electrode which has low thermal expansion coefficient enables to stabilize the ferroelectric o-phase even at ultra-thin HZO film, and TaN layer suppresses the diffusion of W atoms into ferroelectric HZO layer, resulting in reduction of leakage current and giant TER value of 100. In addition, highly asymmetric switching characteristics with rectifying ratio of 1000 is achieved using imprint field effect induced by positive fixed charges nearby bottom interface. The proposed device provides a viable solution for high performance, low power and high-density synaptic devices and TCAM applications.