ANTONIS Lab Research

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Nano-electronic Device

  • [M3D structure device schematics and SEM image]

  • [ID-VG curves for M3D devices]

Recently, Si-based semiconductor devices have reached the limit of scaling, making it difficult to increase the intensity. To solve the problem, many researchers are actively studying monolithic 3D (M3D) structures. The M3D structure device can overcome the limitation of scaling by stacking the device in multiple layers, and it can solve the delay problem caused by the global wiring resistance between the CPU and memory. For channels used for M3D integration, Si, Ge, oxide semiconductors, and 2D materials are used. oxide channel TFTs are BEOL compatible, and low-temperature and large-area processes are possible, therefore oxide channel is suitable for M3D structure integration. We are conducting research on stacking oxide channel TFTs in an M3D structure on Si CMOS ICs. In addition, research on integrating FeTFT memory devices using ferroelectrics is being conducted.

  • [3D Ferroelectric NAND Flash]

  • [Multi-state FeFET based Logic-in-Memory]

This work demonstrates core materials, process and structure approaches such as Zr-rich HfZrO, high pressure (200atm) annealing, high CDE/CFE structures in order to have high performance and high reliability ferroelectric field effect transistor (FeFET) for 3D ferroelectric NAND Flash memory devices. Here, all ferroelectric processes are proceeded using CMOS technology at low temperature (<500℃). Our device presents large memory window (M.W. of >5.5V), 3 bit operation, high program/erase speed (<20ns) and high endurance (>109). In addition, in this work, we present vertically stacked 3D process integration scheme having high CDE/CFE MFMIS structure and the operation scheme for multi-bit NAND Flash memory, which allows to have outstanding memory performances that could be achieved neither by the conventional charge-storage based Flash nor by the previous FeFET based memory devices.

  • [Importance of Thermal Stability of Hafnia Ferroelectrics]

    [Improvement of Thermal Stability of Hafnia Ferroelectrics]

  • [Origins of Thermal Instability]

This work provides a methodology for designing thermally stable hafnia ferroelectric (FE) materials to be taken into account while fabricating 3D memory devices. We reveal the underlying origins for the thermal instability of hafnia FE materials in terms of kinetics and material science. Furthermore, we suggest adopting dopants whose ionic radius is smaller than Hf in the FE matrix as a feasible option to demonstrate a thermally stable hafnia FE material. Using this approach, robust ferroelectricity is achieved even at a subsequent thermal budget (TB) of 750 ℃ for 30 min. The improved thermal stability stems from the reduced formation of both the m-phase and oxygen vacancy (VO) in hafnia FE materials at high TB. The in-depth electrical and material analysis in this study serves a framework for further research into the thermal stability of FE. This work contributes to the commercialization of FE devices by filling the gap between the functionality of FE materials and their process applicability for 3D devices.

  • [Approaches for FeFET with superior MLC operation]

    [Electrical profiles for MFIS/MFMIS FeFET]

  • [MLC operations of FeFETs]

We demonstrate the novel approach to superior multi-level-cell FeFET with a large memory Window(MW) and negligible VT variation toward quadruple-level-cell (QLC) operation. We realized high ferroelectricity in a relatively thick HZO Ferroelectric (FE) layer for FeFET with a large MW (MW α thickness of FE layer (TFE)) based on our understanding of thermodynamics and kinetics. Moreover, weemployed the MFMIS gate stack having a floating gate for FeFET to minimize the VT variation with respect to different distributions of phase&grain size. We applied experimentally obtained materials and electrical data of HZO to TCAD simulation to statistically analyze the impact of materials and gate stack on the MW and the VT variation of FeFET.

  • [Innovative CMOS compatible process for low-temperature crystallization]

The thermal treatment method based on electromagnetic wave induced annealing (EMA) can heat a material by transferring energy in the form of electromagnetic waves as well as heat through the dipole interaction between the material and electromagnetic waves. As a result, EMA can reduce the process temperature and time compared to the conventional annealing processes such as rapid thermal annealing and furnace. In addition, EMA has been attracting attention because it can minimize thermal damage to the underlying device in the large-area vertically stacked high-density device required by the semiconductor market. Our group has technology to control the crystallinity of hafnia ferroelectrics of various compositions and thicknesses through high-pressure annealing of the conventional furnace method. We are currently working on high pressure EMA for hafnia material while considering microwave absorption of hafnia and silicon carbide hybrid annealing. We convince that this approach will bring the breakthrough for low temperature process-based high-speed non-volatile memory and flexible sensor technology.

  • [Ferroelectric Hafnia Capacitors near Morphotrophic Phase Boundary for Memory and Sensors Technology]

Hafnia material system has gained more attention in the recent past for achieving high dielectric constant, low EOT and reduced leakage current. Very recently, morphotropic phase boundary (MPB) has become a novel strategy to enhance the high-κ and scaling down the EOT in hafnia ferroelectrics when compared with traditional high-κ ferroelectrics. The MPB is a mixed crystalline phase, which exists between the phases of ferroelectric (orthorhombic; o-phase) and anti-ferroelectric (tetragonal; t-phase) in the hafnia materials system. Consequently, the dielectric constant (κ) is maximized near the MPB, resulting in a reduced equivalent oxide thickness (EOT). The hafnia material system's MPB phase allows for an increase in the dielectric constant, creating new opportunities for memory & sensors technology and other nano-electronic devices.

  • [AFE/FE (ZrO2/HZO) Bilayer Heterostructures near Morphotrophic Phase Boundary for DRAM technology]

In the present hyper-scaling era, memory technology is advancing owing to the demand for high-performance computing and storage devices. To operate high-performance computing devices, high-density (>16 GB), high-speed(~20 ns), and an excellent reliable (an ultimate endurance of 1016 cycles) memory devices such as DRAMs are required. Very recently, morphotropic phase boundary (MPB) has become a novel strategy to enhance the high-κ and scaling down the EOT in hafnia ferroelectrics when compared with traditional high-κ ferroelectrics. We present a novel approach to achieve lowest EOT (3.8 Å) and high dielectric constant (κ=59) in the vicinity of morphotropic phase boundary (MPB) with AFE/FE hetero-structures and HPA technique. This is the ever lowest value among all reported EOT using CMOS compatible hafnia and TiN electrodes. Kinetically stabilized hafnia films with reduced leakage current density are having significant importance for the future DRAM technology.