CN100530691C - Semiconductor device including high-k insulating layer and method of manufacturing the same - Google Patents

Semiconductor device including high-k insulating layer and method of manufacturing the same Download PDF

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CN100530691C
CN100530691C CNB2006100050218A CN200610005021A CN100530691C CN 100530691 C CN100530691 C CN 100530691C CN B2006100050218 A CNB2006100050218 A CN B2006100050218A CN 200610005021 A CN200610005021 A CN 200610005021A CN 100530691 C CN100530691 C CN 100530691C
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insulating barrier
storage unit
doped region
semiconductor storage
layer
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CN1825628A (en
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田尚勋
崔圣圭
金桢雨
黄显相
韩祯希
崔相武
朴星昊
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Samsung Electronics Co Ltd
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Abstract

A semiconductor memory device a first dopant area and a second dopant area, the first dopant area and the second dopant area disposed in a semiconductor substrate, an insulating layer disposed in contact with the first dopant area and the second dopant area, the insulating layer including a material selected from the group consisting of Hf, Zr, Y, and Ln, and a gate electrode layer disposed on the insulating layer.

Description

The semiconductor device and the manufacture method thereof that comprise high-k insulating layer
Technical field
The disclosure relates to a kind of semiconductor storage unit and manufacture method thereof that comprises high-k (high k) insulating barrier.
Background technology
The development of semiconductor storage unit concentrates on the speed that increases information storage capacity and information record and wipe.Such semiconductor storage unit comprises a large amount of with the interconnective unit storage unit of circuit.
For example each unit cell of the semiconductor storage unit of dynamic random access memory (DRAM) DRAM comprises transistor and capacitor.DRAM be can carry out access fast but for the storage signal have the short volatile memory device of holding time.
The exemplary of volatile memory device is a flash memory.Developed the volatile memory device that various other types, for example silicon-nitride-oxide semiconductor (silicon-nitride-oxide, SNOS) memory device, MRAM, PRAM etc.Flush memory device, SNOS memory device and floating grid polar form memory device use the material with high-k (high k) usually.
Figure 1A and 1B are the sectional views that the technology of making the conventional SNOS memory device with high k material is shown.With reference to Figure 1A, tunneling oxide layer 13, electric charge capture layer 14, obstruct oxide skin(coating) 15 and gate electrode layer 16 are formed on the Semiconductor substrate 11 successively.Tunneling oxide layer 13 can be by SiO 2Form about 30
Figure C20061000502100051
Thickness, electric charge capture layer 14 can be by HfO 2Form, and obstruct oxide skin(coating) 15 can be by Al 2O 3Form about 100
Figure C20061000502100052
Thickness.
Then, the both sides of each of tunneling oxide layer 13, electric charge capture layer 14, obstruct oxide skin(coating) 15 and gate electrode layer 16 all are removed to form grid.As a result, go out the upper surface of Semiconductor substrate 11 in the grid exposed at both sides.
With reference to Figure 1B, by ion implantation, the upper surface of the Semiconductor substrate 11 of grid both sides is mixed by the dopant of for example boron (B) or phosphorus (P).Herein, according to the doping type chosen dopant of Semiconductor substrate 11.In other words, if Semiconductor substrate 11 is n type substrates, the first and second doped region 12a and 12b be injected into belong to III family material with the doped p type dopant.If Semiconductor substrate 11 is p type substrates, the first and second doped region 12a and 12b be injected into belong to V family material with the Doped n-type dopant.
Semiconductor substrate 11 is injected into dopant shown in Figure 1B after, carry out annealing process to activate first and second doped region 12a and the 12b, shown in Fig. 1 C.For this reason, the first and second doped region 12a and the 12b high temperature between about 900 ℃ and 1000 ℃ is heated.The first and second doped region 12a and 12b are become first and second doped region 12a ' and the 12b ' by this high-temperature annealing process crystallization.
Yet above-mentioned high-temperature annealing process also may cause the crystallization that becomes of the high k material in the grid structure that is used in semiconductor storage unit usually.Usually, be under the situation of amorphous in the initial deposition state at high k material, in the semiconductor storage unit course of work, high k material must insulate with gate electrode layer 16.Yet, the material that is used to intercept oxide skin(coating) 15 by the situation of high-temperature annealing process crystallization under, may produce leakage current by the grain boundary district, and may have the characteristic of semiconductor storage unit adverse effect to.
For example, Fig. 2 A and 2B show the characteristic of the memory device of the above-mentioned high-temperature annealing process manufacturing of the employing shown in Figure 1A-1C.
Fig. 2 A shows under oxygen atmosphere, in current-voltage (I-V) characteristic of the conventional semiconductor storage unit of the annealing temperature of 700 ℃, 800 ℃ and 900 ℃.With reference to Fig. 2 A, when voltage during near 0V, current density reduces gradually.Yet current density is still approaching greater than zero value.Particularly, when semiconductor storage unit when 900 ℃ higher temperature is annealed, current density has bigger value.
Fig. 2 B illustrates the semiconductor storage unit made according to the technology shown in above-mentioned Figure 1A and the 1B measured X-ray diffraction (XRD) figure behind the annealing temperature of 700 ℃, 800 ℃, 900 ℃, 950 ℃ and 1000 ℃.With reference to Fig. 2 B, as can be seen along with annealing temperature increases, Al 2O 3The peak becomes remarkable at about 68 °.This peak shows that crystallization takes place.In other words, along with annealing temperature increases, the easier generation of crystallization.
Fig. 2 C illustrates to keep the curve chart of characteristic with respect to annealing temperature according to the semiconductor storage unit of Figure 1A and the described technology manufacturing of 1B.Semiconductor storage unit has the high maintenance value that is less than or equal to " 0.2 " under 800 ℃ or following annealing temperature, but has the low value of keeping under 900 ℃ annealing temperature.
Therefore, as can be seen, the crystallization of the high k material that is caused by high-temperature annealing process has adverse effect to the characteristic of conventional semiconductor storage unit.
Embodiments of the invention have solved these and other shortcoming of routine techniques.
Summary of the invention
The invention provides a kind of semiconductor storage unit, it comprises for example high k material of hafnium silicate (Hf), zirconium silicate (Zr), yttrium silicate (Y) or lanthanide series metal silicate, even make also to keep thermally-stabilised, and the method for making this semiconductor storage unit at the high-temperature annealing process that is used for activating first and second doped regions.
Description of drawings
By the description of reference accompanying drawing to one exemplary embodiment of the present invention, above-mentioned and other specific and advantage of the present invention will become more obvious.
Figure 1A is the sectional view that the conventional method of making the SNOS semiconductor storage unit is shown to 1C.
Fig. 2 A is the curve chart of electrology characteristic that the semiconductor storage unit of Figure 1A-1C is shown.
Fig. 2 B is the curve chart of XRD that the semiconductor storage unit of Figure 1A-1C is shown.
Fig. 2 C illustrates Figure 1A to keep the curve chart of characteristic with respect to annealing temperature to the semiconductor storage unit shown in the 1C.
Fig. 3 A is to illustrate to be used for the sectional view of method that according to embodiments of the invention manufacturing comprises the semiconductor storage unit of high k insulating barrier to 3D.
Fig. 4 illustrates the curve chart of the dielectric constant of Zr or Hf silicate with respect to the atomic percent of Zr or Hf silicate.
Fig. 5 A is the ZrO that the atomic percent with 66: 33 is shown 2And SiO 2The curve chart of the XRD of compound.
Fig. 5 B is the ZrO that the atomic percent with 45: 55 is shown 2And SiO 2The curve chart of the XRD of compound.
Fig. 5 C is the ZrO that the atomic percent with 17: 83 is shown 2And SiO 2The curve chart of the XRD of compound.
Fig. 6 A is the HfO that the atomic percent with 82: 18 is shown 2And SiO 2The curve chart of the XRD of compound.
Fig. 6 B is the HfO that the atomic percent with 57: 43 is shown 2And SiO 2The curve chart of the XRD of compound.
Fig. 6 C is the HfO that the atomic percent with 26: 73 is shown 2And SiO 2The curve chart of the XRD of compound.
Embodiment
Describe with reference to the accompanying drawings according to comprising of some embodiments of the present invention high k insulating barrier semiconductor storage unit and make the method for this semiconductor storage unit.
Fig. 3 A is the sectional view that the manufacture method of the semiconductor storage unit that comprises high k insulating barrier according to some embodiments of the invention is shown to 3D.In the accompanying drawings, for clear and exaggerated the thickness in layer and zone.In the illustrated embodiment, be described as an example with the SONOS memory device.Yet, should be appreciated that, comprise that principle of the present invention in the illustrated embodiment can be applied in other memory devices that comprise high k material, for example flush memory device, floating grid polar form memory etc.
With reference to Fig. 3 A, first oxide skin(coating) 33, electric charge capture layer 34, second oxide skin(coating) 35 and gate electrode layer 36 are formed on the Semiconductor substrate 31 successively.Usually, first oxide skin(coating) 33, electric charge capture layer 34 and second oxide skin(coating) 35 are formed by dielectric material, and have the character of insulator.Herein, in the situation of SONOS memory device, first oxide skin(coating) 33 can be called the tunneling oxide layer, and second oxide skin(coating) 35 can be called the obstruct oxide skin(coating).
According to embodiments of the invention, dielectric layer comprises high-k dielectric material.High-k dielectric material can comprise that hafnium silicate (Hf), zirconium silicate (Zr), yttrium silicate (Y) or lanthanum (Ln) are one or more of metal silicate, and wherein Ln is generally used for claiming any one in 15 kinds of elements (La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb or Lu) in the lanthanide series metal.
Particularly, high-k dielectric material comprises ((Hf, Zr, Y or Ln) O 2) x(SiO 2) 1-x, wherein in the scope of x between 0.03 and 0.26 (0.03≤x≤0.26).In other words, the amount of adding Hf, Zr, Y or the Ln of silicate to can optionally be adjusted between the scope of the atomic percent of 3% atomic percent and 26%.Therefore, as what will describe in detail below, it is thermally-stabilised that semiconductor storage unit can keep in the high-temperature annealing process in making this semiconductor storage unit technology.In certain embodiments, for example the material of aluminium (A1) or nitrogen (N) can add ((Hf, Zr, Y or Ln) O to 2) x(SiO 2) 1-xIn, to guarantee thermal stability.
In optional embodiment, A1 can replace silicon (Si) to be used and is high-k dielectric material.In this case, the chemical formula of high-k dielectric material is ((Hf, Zr, Y or Ln) O 2) x(Al 2O 3) 1-x, wherein (0.03≤x≤0.26).
With reference to Fig. 3 B, the both sides of each of tunneling oxide layer 33, electric charge capture layer 34, obstruct oxide skin(coating) 35 and gate electrode layer 36 are by etching successively, to limit the area of grid of preset width.As a result, expose the upper surface of the Semiconductor substrate 31 of area of grid both sides.Resulting structures shown in Fig. 3 A and the 3B can easily be made by generally well-known semiconductor technology.
With reference to Fig. 3 C, employing ion implantation technology etc. are to the upper surface doping dopant of the exposure of Semiconductor substrate 31.Herein, dopant can optionally use according to the dopant states of Semiconductor substrate 31.If Semiconductor substrate 31 is p type substrates, the upper surface of Semiconductor substrate 31 can mix belong to V family material to form first and second doped region 32a and the 32b.If Semiconductor substrate 31 is n type substrates, the upper surface of Semiconductor substrate 31 can mix and belong to the material of III family, to form first and second doped region 32a and the 32b.
With reference to Fig. 3 D, under the temperature between about 950 ℃ and 1000 ℃, carry out annealing process.If annealing process carries out several seconds to a few minutes, can form what be activated is first and second doped region 32a ' and the 32b ' of crystallization.Annealing process should carry out under 900 ℃ or above temperature, to activate first and second doped region 32a and the 32b as mentioned above.
As explained above, if temperature is greater than or equal to high k material by the temperature of recrystallization (re-crystallized), high k material changes crystalline state into from amorphous state.Therefore, in the situation of conventional SONOS memory device, in intercepting oxide skin(coating) 35,, the grain boundary leaks owing to producing undesirable electric current.Therefore, the electric charge that is trapped in the data storage area moves probably, and device keep deterioration in characteristics.
Yet, according to embodiments of the invention, when high k insulating barrier comprises the silicate of Hf, Zr, Y or lanthanide series metal or is made up of it, even high k insulating barrier also remains on stable amorphous state in high-temperature annealing process.This has prevented the deterioration of the electrical characteristics of semiconductor storage unit.
The characteristic of high k insulating barrier according to some embodiments of the invention further describes with reference to the accompanying drawings.Particularly, with describing Z r silicate or Hf silicate insulating barrier.
Fig. 4 illustrates the figure of the dielectric constant of Zr silicate or Hf silicate with respect to the atomic percent of Zr in the silicate or Hf.With reference to Fig. 4, dielectric constant along with Zr or Hf with respect to the increase of the atomic percent of Si and increase.According to embodiments of the invention, if Zr or Hf add SiO to 2, the atomic percent of Zr or Hf can be 26% or littler.In this case, the dielectric constant of Zr silicate or Hf silicate is slightly smaller than ten (10).Like this, Zr or Hf silicate are to have the SiO of ratio 2The high k material of dielectric constant dielectric constants big, about 3.9.As a result, according to embodiments of the invention, in the scope of the dielectric constant of high k material between 3.9 and 10 (3.9＜k＜10).
Fig. 5 A is the curve chart that illustrates with respect to the XRD of the Zr amount of adding silicate to Fig. 5 C.
Fig. 5 A is the ZrO that is illustrated in the atomic percent with 66: 33 2And SiO 2Sample XRD figure manufactured and that the annealing back is measured under 600 ℃, 800 ℃, 900 ℃ and 1000 ℃ of temperature.With reference to Fig. 5 A, when annealing temperature is high, observed the peak of crystalline characteristics.Particularly, observed ZrO crystal characteristic peak at about 30 °.Therefore, can determine sample crystallization.
Fig. 5 B is the ZrO that is illustrated in the atomic percent with 45: 55 2And SiO 2Manufactured and the XRD figure that the annealing back is measured under 600 ℃, 800 ℃, 900 ℃ and 1000 ℃ of temperature then of sample.With reference to Fig. 5 B, when annealing temperature is high, observed the peak of crystalline characteristics.From the sample of under 900 ℃ and 1000 ℃ of temperature, annealing, observed ZrO crystal characteristic peak at about 30 °.As a result, can determine the crystallization in the manufacturing process of semiconductor storage unit of high k material, in this technology, under 900 ℃ or above temperature, anneal.
Fig. 5 C is the ZrO that is illustrated in the atomic percent with 17: 83 2And SiO 2Manufactured and the XRD figure that the annealing back is measured under 600 ℃, 800 ℃, 900 ℃ and 1000 ℃ of temperature then of sample.With reference to Fig. 5 C, can see, even under high annealing temperature, do not observe yet and have about 30 ° of ZrO crystal characteristic peaks of locating.At about 57 ° of characteristic peaks that observed characteristic peak is the Si substrate.Therefore, when carrying out high annealing, the Zr silicate with the atomic percent in the scope of being instructed by the embodiment of the invention is non-crystallizable, but keeps amorphous.
Fig. 6 A is the curve chart that illustrates with respect to the XRD of the atomic percent of the Hf that adds silicate to 6C.
Fig. 6 A is the HfO that is illustrated in the atomic percent with 82: 18 2And SiO 2The sample manufacturing and the XRD figure that the annealing back is measured under 600 ℃, 800 ℃, 900 ℃ and 1000 ℃ of temperature subsequently.With reference to Fig. 6 A, when annealing temperature is high, clearly observed HfO at about 30 ° 2The crystalline characteristics peak.Therefore, can determine that crystallization carries out.
Fig. 6 B is the HfO that is illustrated in the atomic percent with 57: 43 2And SiO 2Sample manufacturing and the XRD figure that the annealing back is measured under 600 ℃, 800 ℃, 900 ℃ and 1000 ℃ of temperature subsequently.With reference to Fig. 6 B, do not observe characteristic peak 600 ℃ and 800 ℃ of temperature.Therefore, can determine that amorphous state has been held.Yet, under the temperature of 900 ℃ and 1000 ℃, observed HfO at about 30 ° 2Characteristic peak.Therefore, can determine, carry out in these temperature crystallizations.As a result, by crystallization, in this technology, carry out under 900 ℃ or higher temperature by annealing in the manufacturing process of semiconductor storage unit for high k material.
Fig. 6 C is the HfO that is illustrated in the atomic percent with 26: 73 2And SiO 2Sample manufacturing and the XRD figure that the annealing back is measured under 600 ℃, 800 ℃, 900 ℃ and 1000 ℃ of temperature subsequently.With reference to Fig. 6 C, do not observe characteristic peak 600 ℃ and 800 ℃ of temperature.Therefore, can determine that amorphous state has been held.Yet, under the temperature of 900 ℃ and 1000 ℃, observed HfO at about 30 ° 2Characteristic peak.Therefore, carried out in these temperature crystallizations.As a result, by crystallization, in this technology, carry out under 900 ℃ or higher temperature by annealing in the manufacturing process of semiconductor storage unit for high k material.
Therefore, according to embodiments of the invention, it is heat-staple having in the high-temperature annealing process that the Zr of the ratio of component that is less than or equal to 26% atomic percent or Hf silicate carries out under 900 ℃ or above temperature.Therefore, Zr or Hf silicate is not by crystallization but remain amorphous.Herein, the dielectric constant of Zr or Hf silicate remain on " 10 " or below.Even be used as in the situation of dielectric layer at Y silicate or lanthanum family metal (Ln) silicate, also can observe these features.In this case, set up chemical formula " ((Hf, Zr, Y or Ln) O 2) x(SiO 2) 1-x(0.03≤x≤0.26) ".And A1 can replace Si and be used in this chemical formula.In this case, can be expressed as chemical formula " ((Hf, Zr, Y or Ln) O 2) x(Al 2O 3) 1-x(0.03≤x≤0.26) ".
As mentioned above, according to embodiments of the invention, Zr or Hf silicate can be used as the high k material in flush memory device, SONOS memory device, floating grid type memory device or the trapped-charge memory.Therefore, can prevent the crystallization of high k material (ferroelectric layer), to avoid because high-temperature annealing process and to the adverse effect of semiconductor storage unit characteristic.Leakage current can reduce, and the keeping characteristic and also can improve of semiconductor storage unit.Simultaneously, although improve, still can adopt the generally well-known manufacturing process that is used for producing the semiconductor devices according to above-mentioned inventive principle.
The present invention may be embodied as many modes.Be exemplary, nonrestrictive description below to some embodiments of the present invention.
According to some embodiment, semiconductor storage unit comprises first and second doped regions that are formed in the Semiconductor substrate; Be formed on this Semiconductor substrate to contact the insulating barrier of first and second doped regions, this insulating barrier comprises Hf silicate, Zr silicate, Y silicate or lanthanide series metal silicate; And be formed on gate electrode layer on this insulating barrier.
Insulating barrier can have ((Hf, Zr, Y or Ln) O 2) x(SiO 2) 1-xThe component of (0.03≤x≤0.26) and be less than or equal to ten (10) dielectric constant.
Insulating barrier can comprise tunneling oxide layer, data storage layer and the obstruct oxide skin(coating) that forms successively, and wherein one of tunneling oxide layer and obstruct oxide skin(coating) are to have " ((Hf, Zr, Y or Ln) O 2) x(SiO 2) 1-x(0.03≤x≤0.26) " the dielectric layer of chemical formula.
Insulating barrier can comprise A1 or N.
According to some embodiment, the method for making semiconductor storage unit is included in and forms the insulating barrier that comprises Hf silicate, Zr silicate, Y silicate or lanthanide series metal silicate on the Semiconductor substrate; On insulating barrier, form gate electrode layer; Each the both sides of removing insulating barrier and gate electrode layer to be forming gate regions, and expose the upper surface of the Semiconductor substrate of gate regions both sides; With the upper surface of the exposure of dopant dope semiconductor substrates forming first and second doped regions, thereby and anneal and activate first and second doped regions.
Insulating barrier can be by deposit tunneling oxide layer, electric charge capture layer and obstruct oxide skin(coating) form successively on Semiconductor substrate.Herein, tunneling oxide layer or obstruct oxide skin(coating) can be to have chemical formula " ((Hf, Zr, Y or Ln) O 2) x(SiO 2) 1-x(0.03≤x≤0.26) " dielectric layer.
Insulating barrier can have and is less than or equal to ten (10) dielectric constant, and insulating barrier can comprise A1 or N.
According to some embodiments of the present invention, semiconductor storage unit comprises first and second doped regions that are formed on the Semiconductor substrate, is formed on the Semiconductor substrate to contact first and second doped regions and to have ((Hf, Zr, Y or Ln) O 2) x(Al 2O 3) 1-xThe insulating barrier of the component of (0.03≤x≤0.26) and be formed on gate electrode layer on the insulating barrier.
Above preferred embodiment is construed as the exemplary with illustrative of the principle of the present invention that comprises in a preferred embodiment, rather than to the restriction of category of the present invention.For example, though under the situation of SONOS memory device, described preferred embodiment, but the inventive principle that is included in these preferred embodiments can be applied to other memory devices that use high k material, for example flush memory device, floating grid type memory device or trapped-charge memory.Therefore, category of the present invention is not to be limited by the detailed description of inventing, but is defined by the claims.
In addition, for specific embodiments of the invention, described specification comprises one or more references, and each specific embodiment is used to illustrate the inventive principle that one or more the present invention instructs.Should be appreciated that all embodiment comprise at least one foregoing invention principle, and these embodiment can comprise more than the inventive principle shown in.
The application requires the priority of the korean patent application submitted to Korea S Department of Intellectual Property on January 18th, 2005 10-2005-0004455 number.Korean patent application quotes in full herein as a reference for 10-2005-0004455 number.

Claims (22)

1, a kind of semiconductor storage unit comprises:
First doped region and second doped region, described first doped region and described second doped region are arranged in the Semiconductor substrate;
Insulating barrier is provided with to such an extent that contact with described second doped region with described first doped region, and described insulating barrier comprises at least a in Hf silicate, Zr silicate, Y silicate and the Ln silicate; With
Gate electrode layer is arranged on the described insulating barrier,
Wherein, described insulating barrier comprises a material, and this material has chemical formula ((Hf, Zr, Y or Ln) O 2) x(SiO 2) 1-x, 0.03≤x≤0.26 wherein.
2, semiconductor storage unit as claimed in claim 1, described material have greater than 3.9 and are less than or equal to 10 dielectric constant.
3, semiconductor storage unit as claimed in claim 1, described insulating barrier comprises:
The tunneling oxide layer is provided with to such an extent that contact with second doped region with described first doped region;
Data storage layer is arranged on the described tunneling oxide layer; With
Intercept oxide skin(coating), be arranged on the described data storage layer, one of described tunneling oxide layer and described obstruct oxide skin(coating) are made of described material.
4, semiconductor storage unit as claimed in claim 1, described insulating barrier comprises one of Al and N.
5, semiconductor storage unit as claimed in claim 1, described insulating barrier comprises Hf silicate.
6, semiconductor storage unit as claimed in claim 1, described insulating barrier comprises Zr silicate.
7, semiconductor storage unit as claimed in claim 1, described insulating barrier comprises Y silicate.
8, semiconductor storage unit as claimed in claim 1, described insulating barrier comprises Ln silicate.
9, a kind of method of making semiconductor storage unit, this method comprises:
Form insulating barrier on Semiconductor substrate, described insulating barrier comprises select at least a from the group that comprises Hf, Zr, Y and Ln;
On described insulating barrier, form gate electrode layer;
Remove a part of described insulating barrier and a part of described gate electrode layer, with the qualification grid, and exposure is positioned at the upper surface of the described Semiconductor substrate of grid both sides;
With the mix described upper surface of described Semiconductor substrate of dopant, to form first doped region and second doped region; With
The described upper surface of the described Semiconductor substrate of annealing to be activating described first doped region and described second doped region,
Wherein, described insulating barrier comprises a material, and this material has chemical formula ((Hf, Zr, Y or Ln) O 2) x(SiO 2) 1-x, wherein 0.03≤x≤0.26 perhaps has chemical formula ((Hf, Zr, Y or Ln) O 2) x(Al 2O 3) 1-x, 0.03≤x≤0.26 wherein.
10, method as claimed in claim 9 wherein forms described insulating barrier and comprises:
Deposit tunneling oxide layer on described Semiconductor substrate;
Deposit electric charge capture layer on described tunneling oxide layer; With
Deposit intercepts oxide skin(coating) on described electric charge capture layer, and described tunneling oxide layer is made of described material.
11, method as claimed in claim 9 wherein forms described insulating barrier and comprises:
Deposit tunneling oxide layer on described Semiconductor substrate;
Deposit electric charge capture layer on described tunneling oxide layer; With
Deposit intercepts oxide skin(coating) on described electric charge capture layer, and described obstruct oxide skin(coating) is made of described material.
12, method as claimed in claim 9, wherein said insulating barrier have greater than 3.9 and are less than or equal to 10 dielectric constant.
13, method as claimed in claim 9, wherein said insulating barrier comprises one of Al and N.
14, a kind of semiconductor storage unit comprises:
First doped region and second doped region, described first doped region and described second doped region are arranged in the Semiconductor substrate;
Insulating barrier is provided with to such an extent that contact described first doped region and described second doped region, and described insulating barrier comprises the material of selecting from the group that comprises Hf, Zr, Y and Ln; With
Gate electrode layer is arranged on the described insulating barrier,
Wherein, described insulating barrier comprises a material, and this material has chemical formula ((Hf, Zr, Y or Ln) O 2) x(SiO 2) 1-x, wherein 0.03≤x≤0.26 perhaps has chemical formula ((Hf, Zr, Y or Ln) O 2) x(Al 2O 3) 1-x, 0.03≤x≤0.26 wherein.
15, semiconductor storage unit as claimed in claim 14, described insulating barrier comprises:
The tunneling oxide layer, be provided with contact described first doped region and described second doped region;
Data storage layer is arranged on the described tunneling oxide layer; With
Intercept oxide skin(coating), be arranged on the described data storage layer, described tunneling oxide layer is made of described material.
16, semiconductor storage unit as claimed in claim 14, wherein said insulating barrier comprises:
The tunneling oxide layer, be provided with contact described first doped region and described second doped region;
Data storage layer is arranged on the described tunneling oxide layer; With
Intercept oxide skin(coating), be arranged on the described data storage layer, described obstruct oxide skin(coating) is made of described material.
17, semiconductor storage unit as claimed in claim 14, described insulating barrier comprises Hf.
18, semiconductor storage unit as claimed in claim 14, described insulating barrier comprises Zr.
19, semiconductor storage unit as claimed in claim 14, described insulating barrier comprises Y.
20, semiconductor storage unit as claimed in claim 14, described insulating barrier comprises Ln.
21, semiconductor storage unit as claimed in claim 14, the dielectric constant of described material is greater than 3.9 and be less than or equal to 10.
22, semiconductor storage unit as claimed in claim 14, described insulating barrier comprises one of Al and N.
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